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| author | Andreas Konopik <andreas.konopik@efs-auto.de> | 2021-02-11 12:53:29 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2021-03-14 14:41:56 +0100 |
| commit | 9b620609d79ca0e101af024435c5b38b80478969 (patch) | |
| tree | 320d7d0f2514f91cc5f4e3a987cd1a12ec4d0a0a /target/tricore | |
| parent | 4f293079402ad9cd1eae73c256d7adedc0b897b5 (diff) | |
| download | qemu-9b620609d79ca0e101af024435c5b38b80478969.zip qemu-9b620609d79ca0e101af024435c5b38b80478969.tar.gz qemu-9b620609d79ca0e101af024435c5b38b80478969.tar.bz2 | |
tricore: fixed faulty conditions for extr and imask
According to the TC 1.3.1. Architecture Manual [1; page 174], results are
undefined, if pos + width > 32 and not 31 or if width = 0.
We found this error because of a different behavior between qemu-tricore
and the real tricore processor. For pos + width = 32, qemu-tricore did not
generate any intermediate code and ran into a different state compared to
the real hardware.
[1] https://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352
[BK: Add the why to the commit message]
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Message-Id: <20210211115329.8984-2-david.brenken@efs-auto.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore')
| -rw-r--r-- | target/tricore/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 7752630..ebeddf8 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5777,8 +5777,8 @@ static void decode_rcpw_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RCPW_IMASK: CHECK_REG_PAIR(r2); - /* if pos + width > 31 undefined result */ - if (pos + width <= 31) { + /* if pos + width > 32 undefined result */ + if (pos + width <= 32) { tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); } @@ -6999,7 +6999,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RRPW_EXTR: - if (pos + width <= 31) { + if (pos + width <= 32) { /* optimize special cases */ if ((pos == 0) && (width == 8)) { tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); @@ -7021,7 +7021,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) break; case OPC2_32_RRPW_IMASK: CHECK_REG_PAIR(r3); - if (pos + width <= 31) { + if (pos + width <= 32) { tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); } |