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| author | David Hildenbrand <david@redhat.com> | 2018-09-27 15:02:57 +0200 |
|---|---|---|
| committer | Cornelia Huck <cohuck@redhat.com> | 2018-10-04 10:32:39 +0200 |
| commit | 13054739b5838c7ef9d2e6e88a68bbf914d63bfa (patch) | |
| tree | 4217d198399561b5a4786c001c65ab0a1e446884 /target/s390x | |
| parent | bbf6ea3bd961970785a583117ac1c0b84a8ee736 (diff) | |
| download | qemu-13054739b5838c7ef9d2e6e88a68bbf914d63bfa.zip qemu-13054739b5838c7ef9d2e6e88a68bbf914d63bfa.tar.gz qemu-13054739b5838c7ef9d2e6e88a68bbf914d63bfa.tar.bz2 | |
s390x/tcg: store in the TB flags if AFP is enabled
We exit the TB when changing the control registers, so just like PSW
bits, this should always be consistent for a TB.
Using the PSW bit semantic makes things a lot easier compared to
manually defining the spare, shifted bits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20180927130303.12236-4-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x')
| -rw-r--r-- | target/s390x/cpu.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 5e50c3a..8c2320e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -255,6 +255,7 @@ extern const struct VMStateDescription vmstate_s390_cpu; /* PSW defines */ #undef PSW_MASK_PER +#undef PSW_MASK_UNUSED_2 #undef PSW_MASK_DAT #undef PSW_MASK_IO #undef PSW_MASK_EXT @@ -273,6 +274,7 @@ extern const struct VMStateDescription vmstate_s390_cpu; #undef PSW_MASK_ESA_ADDR #define PSW_MASK_PER 0x4000000000000000ULL +#define PSW_MASK_UNUSED_2 0x2000000000000000ULL #define PSW_MASK_DAT 0x0400000000000000ULL #define PSW_MASK_IO 0x0200000000000000ULL #define PSW_MASK_EXT 0x0100000000000000ULL @@ -318,6 +320,9 @@ extern const struct VMStateDescription vmstate_s390_cpu; #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) +/* we'll use some unused PSW positions to store CR flags in tb flags */ +#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) + /* Control register 0 bits */ #define CR0_LOWPROT 0x0000000010000000ULL #define CR0_SECONDARY 0x0000000004000000ULL @@ -364,6 +369,9 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, *pc = env->psw.addr; *cs_base = env->ex_value; *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->cregs[0] & CR0_AFP) { + *flags |= FLAG_MASK_AFP; + } } /* PER bits from control register 9 */ |