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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:49 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 8ef67c663709f5a7d3be239777e65479ac236d23 (patch) | |
| tree | 08d4f651932a27b7ffc6aef2c9ae3ac119b22c59 /target/riscv | |
| parent | 7295b18606602c6b0b841a0f089db7f01b6c7ec1 (diff) | |
| download | qemu-8ef67c663709f5a7d3be239777e65479ac236d23.zip qemu-8ef67c663709f5a7d3be239777e65479ac236d23.tar.gz qemu-8ef67c663709f5a7d3be239777e65479ac236d23.tar.bz2 | |
target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.
riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ecb82b..b005bcb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -403,11 +403,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPU *cpu = RISCV_CPU(obj); - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.ext_g = true; - cpu->cfg.ext_icsr = true; cpu->cfg.ext_zfh = true; cpu->cfg.mmu = true; cpu->cfg.ext_xtheadba = true; |