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| author | Jonathan Behrens <jonathan@fintelia.io> | 2019-10-14 11:45:29 -0400 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-10-28 07:47:29 -0700 |
| commit | 81d2929c41d32af138f3562f5a7b309f6eac7ca7 (patch) | |
| tree | 55d49ccf9aa5958f8b8402174c3e1ecf36db410c /target/riscv | |
| parent | ab9056ff9bdb3f95db6e7a666d10522d289f14ec (diff) | |
| download | qemu-81d2929c41d32af138f3562f5a7b309f6eac7ca7.zip qemu-81d2929c41d32af138f3562f5a7b309f6eac7ca7.tar.gz qemu-81d2929c41d32af138f3562f5a7b309f6eac7ca7.tar.bz2 | |
target/riscv: Make the priv register writable by GDB
Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that
the privilege mode is set to one of them. Once support for the H-extension is
added, this code will also need to properly update the virtualization status
when switching between VU/VS-modes and M-mode.
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/gdbstub.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1f71604..1a7947e 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -387,6 +387,15 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) { + if (n == 0) { +#ifndef CONFIG_USER_ONLY + cs->priv = ldtul_p(mem_buf) & 0x3; + if (cs->priv == PRV_H) { + cs->priv = PRV_S; + } +#endif + return sizeof(target_ulong); + } return 0; } |