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author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-09-25 14:56:59 -0300 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2023-10-12 12:16:39 +1000 |
commit | 7d0c302c53ce7508326092d3ed07497f82961ff7 (patch) | |
tree | 9e5ddd57b0c4bc0f2879c18c1a0d677e10fc4014 /target/riscv | |
parent | 32fa177604a8f0e3be331add04da91fef28bfbbd (diff) | |
download | qemu-7d0c302c53ce7508326092d3ed07497f82961ff7.zip qemu-7d0c302c53ce7508326092d3ed07497f82961ff7.tar.gz qemu-7d0c302c53ce7508326092d3ed07497f82961ff7.tar.bz2 |
target/riscv: make riscv_add_satp_mode_properties() public
This function is used for both accelerators. Make it public, and call it
from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to
split KVM specific code for the KVM accelerator class in the next patch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/cpu.c | 5 | ||||
-rw-r--r-- | target/riscv/cpu.h | 1 | ||||
-rw-r--r-- | target/riscv/kvm.c | 1 |
3 files changed, 4 insertions, 3 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c735001..143fbc1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, satp_map->init |= 1 << satp; } -static void riscv_add_satp_mode_properties(Object *obj) +void riscv_add_satp_mode_properties(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); @@ -1585,12 +1585,11 @@ static void riscv_cpu_add_multiext_prop_array(Object *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); - if (kvm_enabled()) { kvm_riscv_cpu_add_kvm_properties(obj); return; } + riscv_add_satp_mode_properties(obj); #endif riscv_cpu_add_misa_properties(obj); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0afa45a..d4b4ac3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; void riscv_cpu_add_misa_properties(Object *cpu_obj); +void riscv_add_satp_mode_properties(Object *obj); /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index e682a70..e5e9571 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1323,6 +1323,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) DeviceState *dev = DEVICE(obj); riscv_init_user_properties(obj); + riscv_add_satp_mode_properties(obj); riscv_cpu_add_misa_properties(obj); riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); |