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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-10-18 14:32:00 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2021-10-22 07:47:51 +1000 |
| commit | 31dbcff713aa297033a008b5188fbb37abf85f36 (patch) | |
| tree | 85454011f5e3f0da872c05854a982d282e24f9b4 /target/riscv | |
| parent | 61d56494884b0d4bbf78d0561258b3548dea3390 (diff) | |
| download | qemu-31dbcff713aa297033a008b5188fbb37abf85f36.zip qemu-31dbcff713aa297033a008b5188fbb37abf85f36.tar.gz qemu-31dbcff713aa297033a008b5188fbb37abf85f36.tar.bz2 | |
target/riscv: Remove some unused macros
Since commit 1a9540d1f1a
("target/riscv: Drop support for ISA spec version 1.09.1")
these definitions are unused, remove them.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu_bits.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 999187a..3aa2512 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -427,14 +427,6 @@ #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL -/* VM modes (mstatus.vm) privileged ISA 1.9.1 */ -#define VM_1_09_MBARE 0 -#define VM_1_09_MBB 1 -#define VM_1_09_MBBID 2 -#define VM_1_09_SV32 8 -#define VM_1_09_SV39 9 -#define VM_1_09_SV48 10 - /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 |