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authorGiuseppe Musacchio <thatlemon@gmail.com>2019-10-01 18:39:52 +0200
committerPalmer Dabbelt <palmer@sifive.com>2019-10-28 07:47:27 -0700
commit2921343b3df93e4848034ec615c01ee221212c3a (patch)
tree10146679519bfe9eade69487326f6aa6fb0a2c27 /target/riscv
parentc3a28b5d04f3b177befa1235e95e7bb09023f859 (diff)
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linux-user/riscv: Propagate fault address
The CPU loop tagged all the queued signals as QEMU_SI_KILL while it was filling the `_sigfault` part of `siginfo`: this caused QEMU to copy the wrong fields over to the userspace program. Make sure the fault address recorded by the MMU is is stored in the CPU environment structure. In case of memory faults store the exception address into `siginfo`. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/cpu_helper.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 917252f..f13131a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -455,9 +455,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
-#ifndef CONFIG_USER_ONLY
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
+#ifndef CONFIG_USER_ONLY
hwaddr pa = 0;
int prot;
bool pmp_violation = false;
@@ -508,7 +508,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
case MMU_DATA_STORE:
cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
break;
+ default:
+ g_assert_not_reached();
}
+ env->badaddr = address;
cpu_loop_exit_restore(cs, retaddr);
#endif
}