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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-02-07 13:35:58 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-03-06 22:23:09 +0100 |
| commit | 1ea4a06af0f6578e5d0ddcea148503290b1c4907 (patch) | |
| tree | 060b35cfbdf984ec058efb07d1815283b1058dd0 /target/riscv | |
| parent | 36861198754af7577c73cdb19e1e385c933bfdc8 (diff) | |
| download | qemu-1ea4a06af0f6578e5d0ddcea148503290b1c4907.zip qemu-1ea4a06af0f6578e5d0ddcea148503290b1c4907.tar.gz qemu-1ea4a06af0f6578e5d0ddcea148503290b1c4907.tar.bz2 | |
target: Use CPUArchState as interface to target-specific CPU state
While CPUState is our interface with generic code, CPUArchState is
our interface with target-specific code. Use CPUArchState as an
abstract type, defined by each target.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220214183144.27402-13-f4bug@amsat.org>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ba0504..c28cbe6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -98,7 +98,7 @@ enum { #define MAX_RISCV_PMPS (16) -typedef struct CPURISCVState CPURISCVState; +typedef struct CPUArchState CPURISCVState; #if !defined(CONFIG_USER_ONLY) #include "pmp.h" @@ -113,7 +113,7 @@ FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) -struct CPURISCVState { +struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ uint64_t fpr[32]; /* assume both F and D extensions */ @@ -499,7 +499,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_MSTATUS_FS MSTATUS_FS #define TB_FLAGS_MSTATUS_VS MSTATUS_VS -typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" |