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| author | Frank Chang <frank.chang@sifive.com> | 2022-01-05 10:22:44 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:09 +1000 |
| commit | 629ccdaa4e43c39d38d67b5ba1cec2bbedb6104d (patch) | |
| tree | ee97bf0df0b0c594e5d68a9faeb986b4e98efed9 /target/riscv | |
| parent | b3e0204968d4e5cc556aa5e09078dedbd1eee4a3 (diff) | |
| download | qemu-629ccdaa4e43c39d38d67b5ba1cec2bbedb6104d.zip qemu-629ccdaa4e43c39d38d67b5ba1cec2bbedb6104d.tar.gz qemu-629ccdaa4e43c39d38d67b5ba1cec2bbedb6104d.tar.bz2 | |
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5e3f7fd..8d92243 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2254,7 +2254,8 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2292,7 +2293,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_ds(s, a->rd, a->rs2, a->vm); } @@ -2321,7 +2323,8 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2359,7 +2362,8 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dd(s, a->rd, a->rs2, a->vm); } |