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authorRob Bradford <rbradford@rivosinc.com>2023-07-18 14:11:44 +0100
committerAlistair Francis <alistair.francis@wdc.com>2023-07-19 14:37:26 +1000
commit32be32509987fbe42cf5c2fd3cea3c2ad6eae179 (patch)
tree9c4908a65064bca27fc47a0ce57df6f88e389d1c /target/riscv
parenta916dc954bb5d5aebe5bfcc222cbe9f984118442 (diff)
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target/riscv: Fix LMUL check to use VLEN
The previous check was failing with: VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a valid combination. Fix the check to allow valid combinations when VLEN is a multiple of ELEN. From the specification: "In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value. In the standard extensions, SEWMIN=8. For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported." Elsewhere in the specification it makes clear that VLEN>=ELEN. From inspection this new check allows: VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8 VLEN=ELEN=32 1/2, 1/4 for SEW >=8 Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230718131316.12283-2-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/vector_helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cfacf2e..4d06754 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if (lmul & 4) {
- /* Fractional LMUL. */
+ /* Fractional LMUL - check LMUL * VLEN >= SEW */
if (lmul == 4 ||
- cpu->cfg.elen >> (8 - lmul) < sew) {
+ cpu->cfg.vlen >> (8 - lmul) < sew) {
vill = true;
}
}