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authorWeiwei Li <liweiwei@iscas.ac.cn>2022-04-23 10:35:02 +0800
committerAlistair Francis <alistair.francis@wdc.com>2022-04-29 10:47:45 +1000
commit68d19b58f42d2493a3ff1c6dfe02a99f9d4ecfb5 (patch)
tree4428c9ae6748130796bc3f5eca25f82656fe3168 /target/riscv/translate.c
parentc29da5a7fe6a5d3e1719ce9a831076df2eff52d5 (diff)
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target/riscv: rvk: add support for zknd/zkne extension in RV32
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r--target/riscv/translate.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 121ead7..0cd1d9e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1007,6 +1007,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
+#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"