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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-01-28 15:19:22 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-03-01 07:33:27 -1000 |
| commit | 597f9b2d30b612d760f9f48fe04cda29bf628e67 (patch) | |
| tree | 283330c8ee061908b08a229fdedb4bdc6059e1f9 /target/riscv/translate.c | |
| parent | 0ef3d7045b565861496a6cb8460acc5d3bc80744 (diff) | |
| download | qemu-597f9b2d30b612d760f9f48fe04cda29bf628e67.zip qemu-597f9b2d30b612d760f9f48fe04cda29bf628e67.tar.gz qemu-597f9b2d30b612d760f9f48fe04cda29bf628e67.tar.bz2 | |
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
In preparation for returning the number of insns generated
via the same pointer. Adjust only the prototypes so far.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 772f9d7..f9d5d10 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1309,7 +1309,7 @@ static const TranslatorOps riscv_tr_ops = { .disas_log = riscv_tr_disas_log, }; -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, target_ulong pc, void *host_pc) { DisasContext ctx; |