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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-03-07 16:14:00 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | ce3af0bbbcdfa754cd50f278e83a750730a67c25 (patch) | |
| tree | cca4a80788737530a5991021c1118c5077c0cfef /target/riscv/machine.c | |
| parent | 193eb522e4083d8e84c3fae443fd98bc300b95d0 (diff) | |
| download | qemu-ce3af0bbbcdfa754cd50f278e83a750730a67c25.zip qemu-ce3af0bbbcdfa754cd50f278e83a750730a67c25.tar.gz qemu-ce3af0bbbcdfa754cd50f278e83a750730a67c25.tar.bz2 | |
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt
instrutions.
Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/machine.c')
| -rw-r--r-- | target/riscv/machine.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 9c45593..27f430a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -329,6 +329,24 @@ static const VMStateDescription vmstate_pmu_ctr_state = { } }; +static bool jvt_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + + return cpu->cfg.ext_zcmt; +} + +static const VMStateDescription vmstate_jvt = { + .name = "cpu/jvt", + .version_id = 1, + .minimum_version_id = 1, + .needed = jvt_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.jvt, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 7, @@ -395,6 +413,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_envcfg, &vmstate_debug, &vmstate_smstateen, + &vmstate_jvt, NULL } }; |