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authorFrank Chang <frank.chang@sifive.com>2021-12-10 15:57:00 +0800
committerAlistair Francis <alistair.francis@wdc.com>2021-12-20 14:53:31 +1000
commit26086aea0d4f5575c0b66acd05ccb41349f8a32d (patch)
tree9695b84df954fa0be8cf43dd08a0d6d0d4edfdef /target/riscv/insn32.decode
parent5c89e9c0966dd423207bc477fcda9eb454d4308f (diff)
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target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn32.decode')
-rw-r--r--target/riscv/insn32.decode4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3b6524b..1a4a287 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -305,6 +305,10 @@ vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
+# Vector unit-stride mask load/store insns.
+vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
+vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
+
# Vector strided insns.
vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm