From 26086aea0d4f5575c0b66acd05ccb41349f8a32d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:57:00 +0800 Subject: target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'target/riscv/insn32.decode') diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3b6524b..1a4a287 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -305,6 +305,10 @@ vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm +# Vector unit-stride mask load/store insns. +vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2 +vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2 + # Vector strided insns. vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm -- cgit v1.1