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authorBin Meng <bmeng@tinylab.org>2023-02-28 18:40:20 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2023-03-01 16:40:13 -0800
commit28eb8bee83c6223f5921f95844e381fe01ec9e0f (patch)
treec61d80b467e24e808d7a4a82a6b57037fd88fef8 /target/riscv/gdbstub.c
parent0ee342256af9205e7388efdf193a6d8f1ba1a617 (diff)
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target/riscv: gdbstub: Minor change for better readability
Use a variable 'base_reg' to represent cs->gdb_num_regs so that the call to ricsv_gen_dynamic_vector_xml() can be placed in one single line for better readability. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-5-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/gdbstub.c')
-rw-r--r--target/riscv/gdbstub.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index e57372d..704f3d6 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
32, "riscv-32bit-fpu.xml", 0);
}
if (env->misa_ext & RVV) {
+ int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
- ricsv_gen_dynamic_vector_xml(cs,
- cs->gdb_num_regs),
+ ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
switch (env->misa_mxl_max) {