diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:01:43 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:45:25 -0800 |
| commit | bd023ce33b85d73791b7bc78fd04a8115c60995e (patch) | |
| tree | 571dca1fab0b14d1c5abfa5c200ef46110e5ac8b /target/riscv/cpu_helper.c | |
| parent | af1fa0039c799a350bcde07b3d8a71dfde07d11b (diff) | |
| download | qemu-bd023ce33b85d73791b7bc78fd04a8115c60995e.zip qemu-bd023ce33b85d73791b7bc78fd04a8115c60995e.tar.gz qemu-bd023ce33b85d73791b7bc78fd04a8115c60995e.tar.bz2 | |
target/riscv: Add the Hypervisor CSRs to CPUState
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu_helper.c')
0 files changed, 0 insertions, 0 deletions