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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-12 13:10:34 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-07-10 22:29:14 +1000 |
| commit | 318df7238b9f842af96aad01ec183012c8fecab9 (patch) | |
| tree | 7a1a7c1e60875c973c7010443f6103b8c800e220 /target/riscv/cpu_cfg.h | |
| parent | f6f72338d80ec6f15a6b18643797bc10901aadf3 (diff) | |
| download | qemu-318df7238b9f842af96aad01ec183012c8fecab9.zip qemu-318df7238b9f842af96aad01ec183012c8fecab9.tar.gz qemu-318df7238b9f842af96aad01ec183012c8fecab9.tar.bz2 | |
disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_cfg.h')
| -rw-r--r-- | target/riscv/cpu_cfg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0b4fe4b..6b7e736 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -157,6 +157,17 @@ static inline bool has_xthead_p(const RISCVCPUConfig *cfg) return cfg->ext_ ## ext ; \ } +MATERIALISE_EXT_PREDICATE(xtheadba) +MATERIALISE_EXT_PREDICATE(xtheadbb) +MATERIALISE_EXT_PREDICATE(xtheadbs) +MATERIALISE_EXT_PREDICATE(xtheadcmo) +MATERIALISE_EXT_PREDICATE(xtheadcondmov) +MATERIALISE_EXT_PREDICATE(xtheadfmemidx) +MATERIALISE_EXT_PREDICATE(xtheadfmv) +MATERIALISE_EXT_PREDICATE(xtheadmac) +MATERIALISE_EXT_PREDICATE(xtheadmemidx) +MATERIALISE_EXT_PREDICATE(xtheadmempair) +MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) #endif |