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| author | Deepak Gupta <debug@rivosinc.com> | 2024-10-08 15:50:04 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:08 +1000 |
| commit | 98f21c30f5beffc45232721ae79c019df58ae9f1 (patch) | |
| tree | ee399f300ec737fbb37a7f5abf717a61209a4810 /target/riscv/cpu.h | |
| parent | 669b4867495c48cfb302c6500de99f79d38802b6 (diff) | |
| download | qemu-98f21c30f5beffc45232721ae79c019df58ae9f1.zip qemu-98f21c30f5beffc45232721ae79c019df58ae9f1.tar.gz qemu-98f21c30f5beffc45232721ae79c019df58ae9f1.tar.bz2 | |
target/riscv: AMO operations always raise store/AMO fault
This patch adds one more word for tcg compile which can be obtained during
unwind time to determine fault type for original operation (example AMO).
Depending on that, fault can be promoted to store/AMO fault.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-15-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 47e7a91..284b112 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -46,8 +46,13 @@ typedef struct CPUArchState CPURISCVState; /* * RISC-V-specific extra insn start words: * 1: Original instruction opcode + * 2: more information about instruction */ -#define TARGET_INSN_START_EXTRA_WORDS 1 +#define TARGET_INSN_START_EXTRA_WORDS 2 +/* + * b0: Whether a instruction always raise a store AMO or not. + */ +#define RISCV_UW2_ALWAYS_STORE_AMO 1 #define RV(x) ((target_ulong)1 << (x - 'A')) @@ -234,6 +239,8 @@ struct CPUArchState { bool elp; /* shadow stack register for zicfiss extension */ target_ulong ssp; + /* env place holder for extra word 2 during unwind */ + target_ulong excp_uw2; /* sw check code for sw check exception */ target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY |