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| author | Anup Patel <apatel@ventanamicro.com> | 2022-06-30 11:41:49 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:18:32 +0200 |
| commit | 8e2aa21b0a0d434be2f53a9435fec4f63ec192c4 (patch) | |
| tree | 650f5b6d4033a132b0d1ed0682671b968593feba /target/riscv/cpu.h | |
| parent | 946e9bccf12f2bcc3ca471b820738fb22d14fc80 (diff) | |
| download | qemu-8e2aa21b0a0d434be2f53a9435fec4f63ec192c4.zip qemu-8e2aa21b0a0d434be2f53a9435fec4f63ec192c4.tar.gz qemu-8e2aa21b0a0d434be2f53a9435fec4f63ec192c4.tar.bz2 | |
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: dramforever <dramforever@live.com>
Message-Id: <20220630061150.905174-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc0..ffb1a18 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,6 +285,11 @@ struct CPUArchState { /* Signals whether the current exception occurred with two-stage address translation active. */ bool two_stage_lookup; + /* + * Signals whether the current exception occurred while doing two-stage + * address translation for the VS-stage page table walk. + */ + bool two_stage_indirect_lookup; target_ulong scounteren; target_ulong mcounteren; |