From 8e2aa21b0a0d434be2f53a9435fec4f63ec192c4 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Thu, 30 Jun 2022 11:41:49 +0530 Subject: target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis Signed-off-by: Anup Patel Acked-by: dramforever Message-Id: <20220630061150.905174-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target/riscv/cpu.h') diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc0..ffb1a18 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,6 +285,11 @@ struct CPUArchState { /* Signals whether the current exception occurred with two-stage address translation active. */ bool two_stage_lookup; + /* + * Signals whether the current exception occurred while doing two-stage + * address translation for the VS-stage page table walk. + */ + bool two_stage_indirect_lookup; target_ulong scounteren; target_ulong mcounteren; -- cgit v1.1