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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-01 11:17:29 -0400 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:06 +1000 |
| commit | 330d2ae32af9a278bc8aa88d598f7750ff27f3dd (patch) | |
| tree | ba139a94e8a4b885d7178630b8f6a64f044b1c81 /target/riscv/cpu.c | |
| parent | 8a2aca3d79f8719b9cf79fdcdfbb89bc6bdb522a (diff) | |
| download | qemu-330d2ae32af9a278bc8aa88d598f7750ff27f3dd.zip qemu-330d2ae32af9a278bc8aa88d598f7750ff27f3dd.tar.gz qemu-330d2ae32af9a278bc8aa88d598f7750ff27f3dd.tar.bz2 | |
target/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6842626..e530df9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -358,7 +358,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->pc = env->resetvec; env->two_stage_lookup = false; #endif - cs->exception_index = EXCP_NONE; + cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); } |