From 330d2ae32af9a278bc8aa88d598f7750ff27f3dd Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 1 Apr 2021 11:17:29 -0400 Subject: target/riscv: Convert the RISC-V exceptions to an enum Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/riscv/cpu.c') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6842626..e530df9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -358,7 +358,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->pc = env->resetvec; env->two_stage_lookup = false; #endif - cs->exception_index = EXCP_NONE; + cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); } -- cgit v1.1