diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2023-07-29 14:31:36 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-02-23 23:24:43 +1000 |
| commit | f6940474fa0db83e1e56a8d0ab955750815e2ccb (patch) | |
| tree | e7ca60d53ad62b09caa9e67b6d3137c4005d3d65 /target/ppc | |
| parent | 80e28a41479723ad3d5fb092048b7564995f79ef (diff) | |
| download | qemu-f6940474fa0db83e1e56a8d0ab955750815e2ccb.zip qemu-f6940474fa0db83e1e56a8d0ab955750815e2ccb.tar.gz qemu-f6940474fa0db83e1e56a8d0ab955750815e2ccb.tar.bz2 | |
target/ppc: Fix move-to timebase SPR access permissions
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/helper_regs.c | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 94c9a5a..410b39c 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -468,18 +468,33 @@ void register_generic_sprs(PowerPCCPU *cpu) &spr_read_tbl, SPR_NOACCESS, &spr_read_tbl, SPR_NOACCESS, 0x00000000); - spr_register(env, SPR_WR_TBL, "TBL", - &spr_read_tbl, SPR_NOACCESS, - &spr_read_tbl, &spr_write_tbl, - 0x00000000); spr_register(env, SPR_TBU, "TBU", &spr_read_tbu, SPR_NOACCESS, &spr_read_tbu, SPR_NOACCESS, 0x00000000); - spr_register(env, SPR_WR_TBU, "TBU", - &spr_read_tbu, SPR_NOACCESS, - &spr_read_tbu, &spr_write_tbu, - 0x00000000); +#ifndef CONFIG_USER_ONLY + if (env->has_hv_mode) { + spr_register_hv(env, SPR_WR_TBL, "TBL", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbl, + 0x00000000); + spr_register_hv(env, SPR_WR_TBU, "TBU", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbu, + 0x00000000); + } else { + spr_register(env, SPR_WR_TBL, "TBL", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbl, + 0x00000000); + spr_register(env, SPR_WR_TBU, "TBU", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, &spr_write_tbu, + 0x00000000); + } +#endif } void register_non_embedded_sprs(CPUPPCState *env) |