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| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-03-02 06:51:37 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:37 +0100 |
| commit | df489ad69c5fac8f4032d5eff9cc9dcc717253c4 (patch) | |
| tree | 238d8ca5467b7da41aede44240172c0a107d57a0 /target/ppc | |
| parent | 85085bbc63791ab6fa02441c53b86369d70e4f86 (diff) | |
| download | qemu-df489ad69c5fac8f4032d5eff9cc9dcc717253c4.zip qemu-df489ad69c5fac8f4032d5eff9cc9dcc717253c4.tar.gz qemu-df489ad69c5fac8f4032d5eff9cc9dcc717253c4.tar.bz2 | |
target/ppc: move vrl[bhwd] to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-24-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/insn32.decode | 5 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-impl.c.inc | 13 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-ops.c.inc | 6 |
3 files changed, 12 insertions, 12 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 7a9fc1d..d918e2d 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -487,6 +487,11 @@ VSRAW 000100 ..... ..... ..... 01110000100 @VX VSRAD 000100 ..... ..... ..... 01111000100 @VX VSRAQ 000100 ..... ..... ..... 01100000101 @VX +VRLB 000100 ..... ..... ..... 00000000100 @VX +VRLH 000100 ..... ..... ..... 00001000100 @VX +VRLW 000100 ..... ..... ..... 00010000100 @VX +VRLD 000100 ..... ..... ..... 00011000100 @VX + ## Vector Integer Arithmetic Instructions VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 27ed87f..f24b78d 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -834,6 +834,11 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv); TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv); TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv); +TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv) +TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv) +TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv) +TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv) + static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right, bool alg) { @@ -970,16 +975,8 @@ GEN_VXFORM3(vsubeuqm, 31, 0); GEN_VXFORM3(vsubecuq, 31, 0); GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0); -GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1); -GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2); GEN_VXFORM(vrlwmi, 2, 2); -GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ - vrlwmi, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3); GEN_VXFORM(vrldmi, 2, 3); -GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ - vrldmi, PPC_NONE, PPC2_ISA300) GEN_VXFORM_TRANS(vsl, 2, 7); GEN_VXFORM(vrldnm, 2, 7); GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \ diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc index 878bce9..a7acea3 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -133,10 +133,8 @@ GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM(vrlb, 2, 0), -GEN_VXFORM(vrlh, 2, 1), -GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207), +GEN_VXFORM_300(vrlwmi, 2, 2), +GEN_VXFORM_300(vrldmi, 2, 3), GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vpkuhum, 7, 0), |