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| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-05-17 09:39:24 -0300 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-05-26 17:11:32 -0300 |
| commit | c36ab970ac0ce257a6badb30f6a485a81c2289d2 (patch) | |
| tree | be861d81a0a64ce8d15978fe88f3179e08b5bb6f /target/ppc | |
| parent | cf862bee0e0d31de4809ac7bacb1d65ff7e8b9ce (diff) | |
| download | qemu-c36ab970ac0ce257a6badb30f6a485a81c2289d2.zip qemu-c36ab970ac0ce257a6badb30f6a485a81c2289d2.tar.gz qemu-c36ab970ac0ce257a6badb30f6a485a81c2289d2.tar.bz2 | |
target/ppc: declare xvxsigsp helper with call flags
Move xvxsigsp to decodetree, declare helper_xvxsigsp with
TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220517123929.284511-8-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/fpu_helper.c | 2 | ||||
| -rw-r--r-- | target/ppc/helper.h | 2 | ||||
| -rw-r--r-- | target/ppc/insn32.decode | 4 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-impl.c.inc | 18 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-ops.c.inc | 1 |
5 files changed, 23 insertions, 4 deletions
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 55ef4b5..9489e06 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3205,7 +3205,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) return xt; } -void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) +void helper_XVXSIGSP(ppc_vsr_t *xt, ppc_vsr_t *xb) { ppc_vsr_t t = { }; uint32_t exp, i, fraction; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 9be69fa..aed1b24 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -531,7 +531,7 @@ DEF_HELPER_FLAGS_2(XXGENPCVDM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr) DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32) DEF_HELPER_FLAGS_5(XXPERMX, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, tl) DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32) -DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr) +DEF_HELPER_FLAGS_2(XVXSIGSP, TCG_CALL_NO_RWG, void, vsr, vsr) DEF_HELPER_FLAGS_5(XXEVAL, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32) DEF_HELPER_FLAGS_5(XXBLENDVB, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32) DEF_HELPER_FLAGS_5(XXBLENDVH, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index d4c2615..483349f 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -710,6 +710,10 @@ XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2 XVCVSPBF16 111100 ..... 10001 ..... 111011011 .. @XX2 XSCVSPDPN 111100 ..... ----- ..... 101001011 .. @XX2 +## VSX Binary Floating-Point Math Support Instructions + +XVXSIGSP 111100 ..... 01001 ..... 111011011 .. @XX2 + ## VSX Vector Test Least-Significant Bit by Byte Instruction XVTLSBB 111100 ... -- 00010 ..... 111011011 . - @XX2_bf_xb diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 9b4f309..ca11e2c 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2151,7 +2151,23 @@ static void gen_xvxexpdp(DisasContext *ctx) tcg_temp_free_i64(xbl); } -GEN_VSX_HELPER_X2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) +static bool trans_XVXSIGSP(DisasContext *ctx, arg_XX2 *a) +{ + TCGv_ptr t, b; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + t = gen_vsr_ptr(a->xt); + b = gen_vsr_ptr(a->xb); + + gen_helper_XVXSIGSP(t, b); + + tcg_temp_free_ptr(t); + tcg_temp_free_ptr(b); + + return true; +} static void gen_xvxsigdp(DisasContext *ctx) { diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index 52d7ab3..4524c5b 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -156,7 +156,6 @@ GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300), GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300), -GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300), /* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */ #define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \ |