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authorMatheus Ferst <matheus.ferst@eldorado.org.br>2022-03-26 13:52:37 +0100
committerCédric Le Goater <clg@kaod.org>2022-03-26 13:52:37 +0100
commitbc504838ff88b505421dd28841ee298d9cff31d0 (patch)
tree6971c36b833750369e9f3ac10c0a653f1d91aecf /target/ppc
parent3d31fe4d662f13c70eb7e87f29513623ccd76322 (diff)
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target/ppc: fix helper_xvmadd* argument order
When the xsmadd* insns were moved to decodetree, the helper arguments were reordered to better match the PowerISA description. The same macro is used to declare xvmadd* helpers, but the translation macro of these insns was not changed accordingly. Reported-by: Víctor Colombo <victor.colombo@eldorado.org.br> Fixes: e4318ab2e423 ("target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220325111851.718966-1-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc')
-rw-r--r--target/ppc/translate/vsx-impl.c.inc20
1 files changed, 10 insertions, 10 deletions
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index e67fbf2..d1f6333 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1324,31 +1324,31 @@ TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO)
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
- TCGv_ptr xt, xa, b, c; \
+ TCGv_ptr xt, s1, s2, s3; \
if (unlikely(!ctx->vsx_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
xt = gen_vsr_ptr(xT(ctx->opcode)); \
- xa = gen_vsr_ptr(xA(ctx->opcode)); \
+ s1 = gen_vsr_ptr(xA(ctx->opcode)); \
if (ctx->opcode & PPC_BIT32(25)) { \
/* \
* AxT + B \
*/ \
- b = gen_vsr_ptr(xT(ctx->opcode)); \
- c = gen_vsr_ptr(xB(ctx->opcode)); \
+ s2 = gen_vsr_ptr(xB(ctx->opcode)); \
+ s3 = gen_vsr_ptr(xT(ctx->opcode)); \
} else { \
/* \
* AxB + T \
*/ \
- b = gen_vsr_ptr(xB(ctx->opcode)); \
- c = gen_vsr_ptr(xT(ctx->opcode)); \
+ s2 = gen_vsr_ptr(xT(ctx->opcode)); \
+ s3 = gen_vsr_ptr(xB(ctx->opcode)); \
} \
- gen_helper_##name(cpu_env, xt, xa, b, c); \
+ gen_helper_##name(cpu_env, xt, s1, s2, s3); \
tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(xa); \
- tcg_temp_free_ptr(b); \
- tcg_temp_free_ptr(c); \
+ tcg_temp_free_ptr(s1); \
+ tcg_temp_free_ptr(s2); \
+ tcg_temp_free_ptr(s3); \
}
GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)