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| author | Chinmay Rath <rathc@linux.ibm.com> | 2024-04-23 12:02:28 +0530 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-05-24 08:57:50 +1000 |
| commit | 86e6202a57b1ea44e6bd1fdb0faa0ce5aa3d4aab (patch) | |
| tree | 6091a79d0c0f9180dd447b3f22abe5cda8b41c02 /target/ppc | |
| parent | a1faff873ab1b808126a110aa6b3bc6050baa0f1 (diff) | |
| download | qemu-86e6202a57b1ea44e6bd1fdb0faa0ce5aa3d4aab.zip qemu-86e6202a57b1ea44e6bd1fdb0faa0ce5aa3d4aab.tar.gz qemu-86e6202a57b1ea44e6bd1fdb0faa0ce5aa3d4aab.tar.bz2 | |
target/ppc: Make divw[u] handler method decodetree compatible.
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it decodetree compatible, so that the
mentioned insns can be safely move to decodetree specs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/translate.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index cb10e33..277d96a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1737,8 +1737,9 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, } } -static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, - TCGv arg2, int sign, int compute_ov) +static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, + TCGv arg1, TCGv arg2, bool sign, + bool compute_ov, bool compute_rc0) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); @@ -1772,7 +1773,7 @@ static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); } - if (unlikely(Rc(ctx->opcode) != 0)) { + if (unlikely(compute_rc0)) { gen_set_Rc0(ctx, ret); } } @@ -1782,7 +1783,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ { \ gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ - sign, compute_ov); \ + sign, compute_ov, Rc(ctx->opcode)); \ } /* divwu divwu. divwuo divwuo. */ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); |