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| author | Víctor Colombo <victor.colombo@eldorado.org.br> | 2022-09-05 09:37:45 -0300 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-09-20 10:54:06 -0300 |
| commit | 4896c15bc36591436f02c3bfc4c828099be2b1f8 (patch) | |
| tree | 1def301d11fe6734c15e2d6eb707a8d5871d4490 /target/ppc | |
| parent | 6a8654d6c215f410cfd5c7dd853e6cf311156b5f (diff) | |
| download | qemu-4896c15bc36591436f02c3bfc4c828099be2b1f8.zip qemu-4896c15bc36591436f02c3bfc4c828099be2b1f8.tar.gz qemu-4896c15bc36591436f02c3bfc4c828099be2b1f8.tar.bz2 | |
target/ppc: Move fsqrts to decodetree
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220905123746.54659-3-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/insn32.decode | 1 | ||||
| -rw-r--r-- | target/ppc/translate/fp-impl.c.inc | 23 | ||||
| -rw-r--r-- | target/ppc/translate/fp-ops.c.inc | 1 |
3 files changed, 2 insertions, 23 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 33aa27b..a5249ee 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -369,6 +369,7 @@ STFDUX 011111 ..... ...... .... 1011110111 - @X ### Floating-Point Arithmetic Instructions FSQRT 111111 ..... ----- ..... ----- 10110 . @A_tb +FSQRTS 111011 ..... ----- ..... ----- 10110 . @A_tb ### Floating-Point Select Instruction diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index e8359af..7a90c0e 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -281,28 +281,7 @@ static bool do_helper_fsqrt(DisasContext *ctx, arg_A_tb *a, } TRANS(FSQRT, do_helper_fsqrt, gen_helper_fsqrt); - -static void gen_fsqrts(DisasContext *ctx) -{ - TCGv_i64 t0; - TCGv_i64 t1; - if (unlikely(!ctx->fpu_enabled)) { - gen_exception(ctx, POWERPC_EXCP_FPU); - return; - } - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - gen_reset_fpstatus(); - get_fpr(t0, rB(ctx->opcode)); - gen_helper_fsqrts(t1, cpu_env, t0); - set_fpr(rD(ctx->opcode), t1); - gen_compute_fprf_float64(t1); - if (unlikely(Rc(ctx->opcode) != 0)) { - gen_set_cr1_from_fpscr(ctx); - } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} +TRANS(FSQRTS, do_helper_fsqrt, gen_helper_fsqrts); /*** Floating-Point multiply-and-add ***/ /* fmadd - fmadds */ diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc index 38759f5..d4c6c4b 100644 --- a/target/ppc/translate/fp-ops.c.inc +++ b/target/ppc/translate/fp-ops.c.inc @@ -62,7 +62,6 @@ GEN_HANDLER_E(stfdepx, 0x1F, 0x1F, 0x16, 0x00000001, PPC_NONE, PPC2_BOOKE206), GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), -GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |