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| author | Nicholas Piggin <npiggin@gmail.com> | 2024-05-01 23:04:34 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-05-24 08:57:50 +1000 |
| commit | b3cfa2dd2b4dc517b9423bf568a358ac5fdd2752 (patch) | |
| tree | c387144f9d0485b0231a25dde085aed3db44834c /target/ppc/insn32.decode | |
| parent | ab4f174baee4b28b454fc94a7de2978c13a423ac (diff) | |
| download | qemu-b3cfa2dd2b4dc517b9423bf568a358ac5fdd2752.zip qemu-b3cfa2dd2b4dc517b9423bf568a358ac5fdd2752.tar.gz qemu-b3cfa2dd2b4dc517b9423bf568a358ac5fdd2752.tar.bz2 | |
target/ppc: Add ISA v3.1 variants of sync instruction
POWER10 adds a new field to sync for store-store syncs, and some
new variants of the existing syncs that include persistent memory.
Implement the store-store syncs and plwsync/phwsync.
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target/ppc/insn32.decode')
| -rw-r--r-- | target/ppc/insn32.decode | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 6b89804..a180380 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1001,7 +1001,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - # Memory Barrier Instructions -&X_sync l -@X_sync ...... ... l:2 ..... ..... .......... . &X_sync -SYNC 011111 --- .. ----- ----- 1001010110 - @X_sync +&X_sync l sc +@X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync +SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - |