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| author | Chinmay Rath <rathc@linux.ibm.com> | 2024-04-23 12:02:30 +0530 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-05-24 08:57:50 +1000 |
| commit | a81b5c186730fe5a92b645c84e538444a64b93f5 (patch) | |
| tree | bbea3b5f62650398e3dd49090a5f5e908bc65410 /target/ppc/insn32.decode | |
| parent | 2871921d857d3137e160dcb57ae0b48ddc98822f (diff) | |
| download | qemu-a81b5c186730fe5a92b645c84e538444a64b93f5.zip qemu-a81b5c186730fe5a92b645c84e538444a64b93f5.tar.gz qemu-a81b5c186730fe5a92b645c84e538444a64b93f5.tar.bz2 | |
target/ppc: Move neg, darn, mod{sw, uw} to decodetree.
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target/ppc/insn32.decode')
| -rw-r--r-- | target/ppc/insn32.decode | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index c529150..3051792 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -196,6 +196,9 @@ &X_a ra @X_a ...... ra:3 .. ..... ..... .......... . &X_a +&X_tl rt l +@X_tl ...... rt:5 ... l:2 ..... .......... . &X_tl + &XO rt ra rb oe:bool rc:bool @XO ...... rt:5 ra:5 rb:5 oe:1 ......... rc:1 &XO @@ -376,6 +379,11 @@ DIVWU 011111 ..... ..... ..... . 111001011 . @XO DIVWE 011111 ..... ..... ..... . 110101011 . @XO DIVWEU 011111 ..... ..... ..... . 110001011 . @XO +MODSW 011111 ..... ..... ..... 1100001011 - @X +MODUW 011111 ..... ..... ..... 0100001011 - @X +DARN 011111 ..... --- .. ----- 1011110011 - @X_tl +NEG 011111 ..... ..... ----- . 001101000 . @XO_ta + ## Fixed-Point Logical Instructions CFUGED 011111 ..... ..... ..... 0011011100 - @X |