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| author | Roman Kapl <rka@sysgo.com> | 2018-09-21 08:59:07 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-11-08 12:04:40 +1100 |
| commit | 50728199c549467b01609ddbb831237f72c8f3f6 (patch) | |
| tree | b34cccca349829897bdc60c7251e801e3bb38962 /target/ppc/cpu.h | |
| parent | 4de6bb0c02ad3f0ec48f0f84ba1a65ab06e81b86 (diff) | |
| download | qemu-50728199c549467b01609ddbb831237f72c8f3f6.zip qemu-50728199c549467b01609ddbb831237f72c8f3f6.tar.gz qemu-50728199c549467b01609ddbb831237f72c8f3f6.tar.bz2 | |
target/ppc: add external PID support
External PID is a mechanism present on BookE 2.06 that enables application to
store/load data from different address spaces. There are special version of some
instructions, which operate on alternate address space, which is specified in
the EPLC/EPSC regiser.
This implementation uses two additional MMU modes (mmu_idx) to provide the
address space for the load and store instructions. The QEMU TLB fill code was
modified to recognize these MMU modes and use the values in EPLC/EPSC to find
the proper entry in he PPC TLB. These two QEMU TLBs are also flushed on each
write to EPLC/EPSC.
Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep
dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx
stwepx.
Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx
stvepxl.
Signed-off-by: Roman Kapl <rka@sysgo.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu.h')
| -rw-r--r-- | target/ppc/cpu.h | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b5b8f6f..ab68abe 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -918,6 +918,19 @@ enum { /* number of possible TLBs */ #define BOOKE206_MAX_TLBN 4 +#define EPID_EPID_SHIFT 0x0 +#define EPID_EPID 0xFF +#define EPID_ELPID_SHIFT 0x10 +#define EPID_ELPID 0x3F0000 +#define EPID_EGS 0x20000000 +#define EPID_EGS_SHIFT 29 +#define EPID_EAS 0x40000000 +#define EPID_EAS_SHIFT 30 +#define EPID_EPR 0x80000000 +#define EPID_EPR_SHIFT 31 +/* We don't support EGS and ELPID */ +#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR) + /*****************************************************************************/ /* Server and Embedded Processor Control */ @@ -947,7 +960,16 @@ struct ppc_radix_page_info { /*****************************************************************************/ /* The whole PowerPC CPU context */ -#define NB_MMU_MODES 8 + +/* PowerPC needs eight modes for different hypervisor/supervisor/guest + + * real/paged mode combinations. The other two modes are for external PID + * load/store. + */ +#define NB_MMU_MODES 10 +#define MMU_MODE8_SUFFIX _epl +#define MMU_MODE9_SUFFIX _eps +#define PPC_TLB_EPID_LOAD 8 +#define PPC_TLB_EPID_STORE 9 #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 |