diff options
| author | Daniel Henrique Barboza <danielhb413@gmail.com> | 2021-12-17 17:57:19 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2021-12-17 17:57:19 +0100 |
| commit | 1f26c75191178a9c652bc98afbefa00c0d4fb486 (patch) | |
| tree | 6fe63218390a47c7a52376bfa7e216ce834ebbac /target/ppc/cpu.h | |
| parent | 7aeac354a6925afcec684e985d56e612f9e81b2d (diff) | |
| download | qemu-1f26c75191178a9c652bc98afbefa00c0d4fb486.zip qemu-1f26c75191178a9c652bc98afbefa00c0d4fb486.tar.gz qemu-1f26c75191178a9c652bc98afbefa00c0d4fb486.tar.bz2 | |
PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The following operations happens during an EBB:
- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).
The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].
This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.
[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/cpu.h')
| -rw-r--r-- | target/ppc/cpu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b047352..fc66c35 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -392,6 +392,19 @@ typedef enum { /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ #define CTRL_RUN PPC_BIT(63) +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) +#define BESCR_INVALID PPC_BITMASK(32, 33) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) |