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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:23:51 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-25 17:14:07 +0300 |
| commit | 8b81968c1cf351430dad66a1b36420f431243842 (patch) | |
| tree | 1ba710e8ade4b755d15bd89b8157c0d8cd4d9b01 /target/openrisc/cpu.h | |
| parent | 673d8215415dc0c13e96b8d757102d942916d1b2 (diff) | |
| download | qemu-8b81968c1cf351430dad66a1b36420f431243842.zip qemu-8b81968c1cf351430dad66a1b36420f431243842.tar.gz qemu-8b81968c1cf351430dad66a1b36420f431243842.tar.bz2 | |
other architectures: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/openrisc/cpu.h')
| -rw-r--r-- | target/openrisc/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 92c38f5..ce4d605 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -290,7 +290,7 @@ typedef struct CPUArchState { int is_counting; uint32_t picmr; /* Interrupt mask register */ - uint32_t picsr; /* Interrupt contrl register*/ + uint32_t picsr; /* Interrupt control register */ #endif } CPUOpenRISCState; |