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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-21 08:16:59 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 08:16:41 -0700 |
| commit | 8036281527e5bdc2ebeca53a592115dcfa605245 (patch) | |
| tree | 10be3f7b151037a50c2b315b840404bf40656a6b /target/nios2 | |
| parent | 9d63656354d7cdac6a4b2cafa8243ede4a551a56 (diff) | |
| download | qemu-8036281527e5bdc2ebeca53a592115dcfa605245.zip qemu-8036281527e5bdc2ebeca53a592115dcfa605245.tar.gz qemu-8036281527e5bdc2ebeca53a592115dcfa605245.tar.bz2 | |
target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE
WE is the architectural name of the field, not WR.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-29-richard.henderson@linaro.org>
Diffstat (limited to 'target/nios2')
| -rw-r--r-- | target/nios2/cpu.h | 2 | ||||
| -rw-r--r-- | target/nios2/helper.c | 4 | ||||
| -rw-r--r-- | target/nios2/mmu.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index bfa86ed..54bb6cd 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -134,7 +134,7 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WR (1 << 18) +#define CR_TLBMISC_WE (1 << 18) #define CR_TLBMISC_PID_SHIFT 4 #define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) #define CR_TLBMISC_DBL (1 << 3) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index c2d0afe..31d83e0 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -69,7 +69,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; env->regs[R_EA] = env->pc + 4; env->pc = cpu->fast_tlb_miss_addr; @@ -104,7 +104,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE; } env->regs[R_EA] = env->pc + 4; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 826cd2a..0f33ea5 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,7 +95,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) FIELD_EX32(v, CR_TLBACC, PFN)); /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ - if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { + if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; @@ -133,7 +133,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, (v & CR_TLBMISC_RD) ? 'R' : '.', - (v & CR_TLBMISC_WR) ? 'W' : '.', + (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 'P' : '.', |