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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-01-28 02:08:39 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-02-21 19:42:34 +0100
commit48b28c6a8e9ff64498efa244b1b3ee1bbcd01202 (patch)
treef554141d4af7e949795b7c08e9734a62fe80f463 /target/mips
parent1190c53e822a287f2767ebddf792d290dd760db0 (diff)
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target/mips: Let cpu_mips_translate_address() take MMUAccessType arg
The single caller, do_translate_address(), passes MMUAccessType to cpu_mips_translate_address(). Let the prototype use it as argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-10-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
-rw-r--r--target/mips/internal.h2
-rw-r--r--target/mips/tlb_helper.c6
2 files changed, 4 insertions, 4 deletions
diff --git a/target/mips/internal.h b/target/mips/internal.h
index d09afde..34915c2 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -146,7 +146,7 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
- int rw);
+ MMUAccessType access_type);
#endif
#define cpu_signal_handler cpu_mips_signal_handler
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 9216c7a..9bb6358 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -903,17 +903,17 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#ifndef CONFIG_USER_ONLY
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
- int rw)
+ MMUAccessType access_type)
{
hwaddr physical;
int prot;
int ret = 0;
/* data access */
- ret = get_physical_address(env, &physical, &prot, address, rw,
+ ret = get_physical_address(env, &physical, &prot, address, access_type,
cpu_mmu_index(env, false));
if (ret != TLBRET_MATCH) {
- raise_mmu_exception(env, address, rw, ret);
+ raise_mmu_exception(env, address, access_type, ret);
return -1LL;
} else {
return physical;