diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-02 00:11:25 -0700 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-28 10:13:42 +0530 |
commit | 8ec7e3c53d48c61e31dd251b84a2b8190a14542d (patch) | |
tree | ec68ebf0e3cc334babb1d5c6b3d23efdf520108e /target/mips/tcg | |
parent | a638af09b6c6b1259803a377a53ef242c5af6af5 (diff) | |
download | qemu-8ec7e3c53d48c61e31dd251b84a2b8190a14542d.zip qemu-8ec7e3c53d48c61e31dd251b84a2b8190a14542d.tar.gz qemu-8ec7e3c53d48c61e31dd251b84a2b8190a14542d.tar.bz2 |
target/mips: Use an exception for semihosting
Within do_interrupt, we hold the iothread lock, which
is required for Chardev access for the console, and for
the round trip for use_gdb_syscalls().
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/tcg')
-rw-r--r-- | target/mips/tcg/exception.c | 1 | ||||
-rw-r--r-- | target/mips/tcg/micromips_translate.c.inc | 6 | ||||
-rw-r--r-- | target/mips/tcg/mips16e_translate.c.inc | 2 | ||||
-rw-r--r-- | target/mips/tcg/nanomips_translate.c.inc | 4 | ||||
-rw-r--r-- | target/mips/tcg/sysemu/mips-semi.c | 4 | ||||
-rw-r--r-- | target/mips/tcg/sysemu/tlb_helper.c | 4 | ||||
-rw-r--r-- | target/mips/tcg/sysemu_helper.h.inc | 2 | ||||
-rw-r--r-- | target/mips/tcg/tcg-internal.h | 2 | ||||
-rw-r--r-- | target/mips/tcg/translate.c | 12 |
9 files changed, 17 insertions, 20 deletions
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 0b21e08..2bd77a6 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -125,6 +125,7 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_TLBRI] = "TLB read-inhibit", [EXCP_MSADIS] = "MSA disabled", [EXCP_MSAFPE] = "MSA floating point", + [EXCP_SEMIHOST] = "Semihosting", }; const char *mips_exception_name(int32_t exception) diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc index fc6ede7..274caf2 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -826,7 +826,7 @@ static void gen_pool16c_insn(DisasContext *ctx) break; case SDBBP16: if (is_uhi(extract32(ctx->opcode, 0, 4))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { /* * XXX: not clear which exception should be raised @@ -942,7 +942,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx) case R6_SDBBP16: /* SDBBP16 */ if (is_uhi(extract32(ctx->opcode, 6, 4))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { generate_exception(ctx, EXCP_RI); @@ -1311,7 +1311,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) break; case SDBBP: if (is_uhi(extract32(ctx->opcode, 16, 10))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc index f57e0a5..0a3ba25 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -952,7 +952,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx) break; case RR_SDBBP: if (is_uhi(extract32(ctx->opcode, 5, 6))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { /* * XXX: not clear which exception should be raised diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc index c0ba2bf..ecb0ebe 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -3695,7 +3695,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SDBBP: if (is_uhi(extract32(ctx->opcode, 0, 19))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { gen_reserved_instruction(ctx); @@ -4634,7 +4634,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx) break; case NM_SDBBP16: if (is_uhi(extract32(ctx->opcode, 0, 3))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { gen_reserved_instruction(ctx); diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c index 6d6296e..ac12c80 100644 --- a/target/mips/tcg/sysemu/mips-semi.c +++ b/target/mips/tcg/sysemu/mips-semi.c @@ -20,10 +20,10 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/log.h" -#include "exec/helper-proto.h" #include "semihosting/softmmu-uaccess.h" #include "semihosting/semihost.h" #include "semihosting/console.h" +#include "internal.h" typedef enum UHIOp { UHI_exit = 1, @@ -238,7 +238,7 @@ static int copy_argn_to_target(CPUMIPSState *env, int arg_num, unlock_user(p, gpr, 0); \ } while (0) -void helper_do_semihosting(CPUMIPSState *env) +void mips_semihosting(CPUMIPSState *env) { target_ulong *gpr = env->active_tc.gpr; const UHIOp op = gpr[25]; diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 73254d1..57ffad2 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -1053,6 +1053,10 @@ void mips_cpu_do_interrupt(CPUState *cs) } offset = 0x180; switch (cs->exception_index) { + case EXCP_SEMIHOST: + cs->exception_index = EXCP_NONE; + mips_semihosting(env); + return; case EXCP_DSS: env->CP0_Debug |= 1 << CP0DB_DSS; /* diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc index 4353a96..af585b5 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -9,8 +9,6 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ -DEF_HELPER_1(do_semihosting, void, env) - /* CP0 helpers */ DEF_HELPER_1(mfc0_mvpcontrol, tl, env) DEF_HELPER_1(mfc0_mvpconf0, tl, env) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 993720b..1d27fa2 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -62,6 +62,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +void mips_semihosting(CPUMIPSState *env); + #endif /* !CONFIG_USER_ONLY */ #endif diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 5f460fb..d9d7692 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -12094,14 +12094,6 @@ static inline bool is_uhi(int sdbbp_code) #endif } -#ifdef CONFIG_USER_ONLY -/* The above should dead-code away any calls to this..*/ -static inline void gen_helper_do_semihosting(void *env) -{ - g_assert_not_reached(); -} -#endif - void gen_ldxs(DisasContext *ctx, int base, int index, int rd) { TCGv t0 = tcg_temp_new(); @@ -13910,7 +13902,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) break; case R6_OPC_SDBBP: if (is_uhi(extract32(ctx->opcode, 6, 20))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { gen_reserved_instruction(ctx); @@ -14322,7 +14314,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) break; case OPC_SDBBP: if (is_uhi(extract32(ctx->opcode, 6, 20))) { - gen_helper_do_semihosting(cpu_env); + generate_exception_end(ctx, EXCP_SEMIHOST); } else { /* * XXX: not clear which exception should be raised |