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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-12 20:08:32 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-11-03 05:52:49 -0300 |
| commit | 297289dca84c7a6a945b1ce94df472b5a0b6cfea (patch) | |
| tree | 30665e4be07e4aadd5a2eec34a930e57541aa10f /target/mips/tcg/translate.c | |
| parent | 2cb2674698ec1227cf8a6d8fd28925b6fdd948a2 (diff) | |
| download | qemu-297289dca84c7a6a945b1ce94df472b5a0b6cfea.zip qemu-297289dca84c7a6a945b1ce94df472b5a0b6cfea.tar.gz qemu-297289dca84c7a6a945b1ce94df472b5a0b6cfea.tar.bz2 | |
target/mips: Convert Loongson DIV.G opcodes to decodetree
DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
'is_double' argument so it can generate DIV.G (divide 32-bit
signed integers).
With this commit we explicit the template used to generate
opcode for 32/64-bit word variants. Next commits will be less
verbose by providing both variants at once.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20241026175349.84523-6-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target/mips/tcg/translate.c')
| -rw-r--r-- | target/mips/tcg/translate.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 73445dd..1c38e89 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -332,7 +332,6 @@ enum { OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2, OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2, OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2, - OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2, OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2, OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2, OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2, @@ -370,7 +369,6 @@ enum { /* Loongson 2E */ OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3, OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3, - OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3, OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3, OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3, OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3, @@ -3613,28 +3611,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); break; - case OPC_DIV_G_2E: - case OPC_DIV_G_2F: - { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGLabel *l3 = gen_new_label(); - tcg_gen_ext32s_tl(t0, t0); - tcg_gen_ext32s_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - tcg_gen_movi_tl(cpu_gpr[rd], 0); - tcg_gen_br(l3); - gen_set_label(l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); - tcg_gen_mov_tl(cpu_gpr[rd], t0); - tcg_gen_br(l3); - gen_set_label(l2); - tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - gen_set_label(l3); - } - break; case OPC_DIVU_G_2E: case OPC_DIVU_G_2F: { @@ -13598,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_MUL: gen_arith(ctx, op1, rd, rs, rt); break; - case OPC_DIV_G_2F: case OPC_DIVU_G_2F: case OPC_MULT_G_2F: case OPC_MULTU_G_2F: @@ -13771,7 +13746,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_DIV_G_2E: case OPC_DIVU_G_2E: case OPC_MOD_G_2E: case OPC_MODU_G_2E: |