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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2024-10-26 14:15:26 -0300
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-11-03 05:49:12 -0300
commit1b63c0b7a5879f7bbea4740697932706446b1ad9 (patch)
tree705833970973b42a74e0155daff278c4e30d1d44 /target/mips/tcg/translate.c
parent5d3d52229b19509eaace662096a52dc91f712fc1 (diff)
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target/mips: Extract decode_64bit_enabled() helper
Extract the decode_64bit_enabled() helper which detects whether CPUs can run 64-bit instructions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241026175349.84523-2-philmd@linaro.org>
Diffstat (limited to 'target/mips/tcg/translate.c')
-rw-r--r--target/mips/tcg/translate.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index d92fc41..6c881af 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1645,13 +1645,18 @@ static inline void check_ps(DisasContext *ctx)
check_cp1_64bitmode(ctx);
}
+bool decode_64bit_enabled(DisasContext *ctx)
+{
+ return ctx->hflags & MIPS_HFLAG_64;
+}
+
/*
* This code generates a "reserved instruction" exception if cpu is not
* 64-bit or 64-bit instructions are not enabled.
*/
void check_mips_64(DisasContext *ctx)
{
- if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
+ if (unlikely((TARGET_LONG_BITS != 64) || !decode_64bit_enabled(ctx))) {
gen_reserved_instruction(ctx);
}
}