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authorRichard Henderson <richard.henderson@linaro.org>2023-02-25 17:46:36 -1000
committerRichard Henderson <richard.henderson@linaro.org>2023-03-13 06:44:37 -0700
commit0bcc6b4cfd46d7c0895d6d64dccebf120a509c6d (patch)
treeeba854f107d882b98c96eb86584a0b2374d05289 /target/mips/tcg/translate.c
parent0694cd597db9a8595aaf5da5afb5fd670dd358d7 (diff)
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target/mips: Avoid tcg_const_tl in gen_r6_ld
Allocate a separate temp for modification. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/tcg/translate.c')
-rw-r--r--target/mips/tcg/translate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 7018c42..bbc2212 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2964,8 +2964,8 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
static inline void gen_r6_ld(target_long addr, int reg, int memidx,
MemOp memop)
{
- TCGv t0 = tcg_const_tl(addr);
- tcg_gen_qemu_ld_tl(t0, t0, memidx, memop);
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_qemu_ld_tl(t0, tcg_constant_tl(addr), memidx, memop);
gen_store_gpr(t0, reg);
}