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| author | Marcin Nowakowski <marcin.nowakowski@fungible.com> | 2021-05-26 11:35:06 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2022-06-11 11:34:12 +0200 |
| commit | a6bc80f7b11188d86010a2d511498fba2fe4b629 (patch) | |
| tree | ca4799384de1774e3fbd2c2f9ce477d3b616247d /target/mips/tcg/sysemu | |
| parent | 30796f556790631c86c733ab06756981be0e1def (diff) | |
| download | qemu-a6bc80f7b11188d86010a2d511498fba2fe4b629.zip qemu-a6bc80f7b11188d86010a2d511498fba2fe4b629.tar.gz qemu-a6bc80f7b11188d86010a2d511498fba2fe4b629.tar.bz2 | |
target/mips: Fix WatchHi.M handling
bit 31 (M) of WatchHiN register is a read-only register indicating
whether the next WatchHi register is present. It must not be reset
during user writes to the register.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: David Daney <david.daney@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com>
Message-Id: <20220511212953.74738-1-philmd@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/sysemu')
| -rw-r--r-- | target/mips/tcg/sysemu/cp0_helper.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index aae2af6..5da1124 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1396,10 +1396,11 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) { uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID); + uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */ if ((env->CP0_Config5 >> CP0C5_MI) & 1) { mask |= 0xFFFFFFFF00000000ULL; /* MMID */ } - env->CP0_WatchHi[sel] = arg1 & mask; + env->CP0_WatchHi[sel] = m_bit | (arg1 & mask); env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); } |