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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-29 20:06:13 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-06-24 16:48:08 +0200 |
| commit | f5c6ee0c6b7b4b79b52a1614a808633dbb694de4 (patch) | |
| tree | 455688d123badd6669785d9e3a65323021d357a6 /target/mips/tcg/msa.decode | |
| parent | 525ea877b27d933eaac69b32c75b8861779811cf (diff) | |
| download | qemu-f5c6ee0c6b7b4b79b52a1614a808633dbb694de4.zip qemu-f5c6ee0c6b7b4b79b52a1614a808633dbb694de4.tar.gz qemu-f5c6ee0c6b7b4b79b52a1614a808633dbb694de4.tar.bz2 | |
target/mips: Merge msa32/msa64 decodetree definitions
We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210617174636.2902654-3-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/msa.decode')
| -rw-r--r-- | target/mips/tcg/msa.decode | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode new file mode 100644 index 0000000..bf132e3 --- /dev/null +++ b/target/mips/tcg/msa.decode @@ -0,0 +1,31 @@ +# MIPS SIMD Architecture Module instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume IV-j +# - The MIPS32 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00866-2B-MSA32-AFP-01.12) +# - The MIPS64 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00868-1D-MSA64-AFP-01.12) + +&rtype rs rt rd sa + +&msa_bz df wt s16 + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype +@bz ...... ... .. wt:5 s16:16 &msa_bz df=3 +@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz + +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa + +BZ_V 010001 01011 ..... ................ @bz +BNZ_V 010001 01111 ..... ................ @bz + +BZ_x 010001 110 .. ..... ................ @bz_df +BNZ_x 010001 111 .. ..... ................ @bz_df + +MSA 011110 -------------------------- |