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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-19 08:47:29 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
| commit | 4701d23aef1d096da20b46ce817e30f81bd01b4b (patch) | |
| tree | 61decdb98299d4ee3ea490259c6601382bc481d4 /target/mips/tcg/msa.decode | |
| parent | b8e74816ec8ee7efdce6aa290cd18c937b317133 (diff) | |
| download | qemu-4701d23aef1d096da20b46ce817e30f81bd01b4b.zip qemu-4701d23aef1d096da20b46ce817e30f81bd01b4b.tar.gz qemu-4701d23aef1d096da20b46ce817e30f81bd01b4b.tar.bz2 | |
target/mips: Convert MSA BIT instruction format to decodetree
Convert instructions with an immediate bit index and
data format df/m to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-11-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/msa.decode')
| -rw-r--r-- | target/mips/tcg/msa.decode | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index cd2b618..3d6c6fa 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -16,6 +16,10 @@ &msa_bz df wt sa &msa_ldi df wd sa &msa_i df wd ws sa +&msa_bit df wd ws m + +%bit_df 16:7 !function=bit_df +%bit_m 16:7 !function=bit_m @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @@ -23,6 +27,7 @@ @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi +@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa @@ -48,5 +53,19 @@ BNZ 010001 111 .. ..... ................ @bz LDI 011110 110 .. .......... ..... 000111 @ldi + SLLI 011110 000 ....... ..... ..... 001001 @bit + SRAI 011110 001 ....... ..... ..... 001001 @bit + SRLI 011110 010 ....... ..... ..... 001001 @bit + BCLRI 011110 011 ....... ..... ..... 001001 @bit + BSETI 011110 100 ....... ..... ..... 001001 @bit + BNEGI 011110 101 ....... ..... ..... 001001 @bit + BINSLI 011110 110 ....... ..... ..... 001001 @bit + BINSRI 011110 111 ....... ..... ..... 001001 @bit + + SAT_S 011110 000 ....... ..... ..... 001010 @bit + SAT_U 011110 001 ....... ..... ..... 001010 @bit + SRARI 011110 010 ....... ..... ..... 001010 @bit + SRLRI 011110 011 ....... ..... ..... 001010 @bit + MSA 011110 -------------------------- } |