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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2018-10-16 12:09:54 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 45ebdd24c3de158890ce390df39855a891e80701 (patch) | |
| tree | 0eae986ff87ebfabdc94cd9108585845ed7c4038 /target/mips/cpu.h | |
| parent | f9c9cd63e3dd84c5f052deec880ec92046bbe305 (diff) | |
| download | qemu-45ebdd24c3de158890ce390df39855a891e80701.zip qemu-45ebdd24c3de158890ce390df39855a891e80701.tar.gz qemu-45ebdd24c3de158890ce390df39855a891e80701.tar.bz2 | |
target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)
Distribute bits 56-63 vendor-specific ASEs as follows:
- bits 0-31 MIPS base instruction sets
- bits 32-47 MIPS ASEs
- bits 48-55 vendor-specific base instruction sets
- bits 56-63 vendor-specific ASEs
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/cpu.h')
0 files changed, 0 insertions, 0 deletions