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| author | Stefan Markovic <smarkovic@wavecomp.com> | 2018-08-02 16:15:53 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-08-16 19:18:45 +0200 |
| commit | 25beba9bf76a677747b779e997c6540677a38311 (patch) | |
| tree | 6c6b3a9cae1856eb5bf988ed44aa70c2319a95be /target/mips/cpu.h | |
| parent | 0413d7a55a8161ebd33541ba1df4285bf180c583 (diff) | |
| download | qemu-25beba9bf76a677747b779e997c6540677a38311.zip qemu-25beba9bf76a677747b779e997c6540677a38311.tar.gz qemu-25beba9bf76a677747b779e997c6540677a38311.tar.bz2 | |
target/mips: Add CP0 BadInstrX register
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target/mips/cpu.h')
| -rw-r--r-- | target/mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 77c638c..009202c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -323,6 +323,7 @@ struct CPUMIPSState { target_ulong CP0_BadVAddr; uint32_t CP0_BadInstr; uint32_t CP0_BadInstrP; + uint32_t CP0_BadInstrX; int32_t CP0_Count; target_ulong CP0_EntryHi; #define CP0EnHi_EHINV 10 |