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| author | Richard Henderson <rth@twiddle.net> | 2016-11-16 10:58:52 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:06:11 -0800 |
| commit | 5318420c62b6f6ce0bb7cfcf115fc21055015f90 (patch) | |
| tree | d7d0db2f8170ddc80c5a2c8d7dd4b54699a3ee02 /target/microblaze | |
| parent | 272694a29dc3ed2ed675e03194d33485a2902f0a (diff) | |
| download | qemu-5318420c62b6f6ce0bb7cfcf115fc21055015f90.zip qemu-5318420c62b6f6ce0bb7cfcf115fc21055015f90.tar.gz qemu-5318420c62b6f6ce0bb7cfcf115fc21055015f90.tar.bz2 | |
target-microblaze: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/microblaze')
| -rw-r--r-- | target/microblaze/helper.h | 1 | ||||
| -rw-r--r-- | target/microblaze/op_helper.c | 5 | ||||
| -rw-r--r-- | target/microblaze/translate.c | 2 |
3 files changed, 1 insertions, 7 deletions
diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h index bd13826..71a6c08 100644 --- a/target/microblaze/helper.h +++ b/target/microblaze/helper.h @@ -3,7 +3,6 @@ DEF_HELPER_1(debug, void, env) DEF_HELPER_FLAGS_3(carry, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(cmp, i32, i32, i32) DEF_HELPER_2(cmpu, i32, i32, i32) -DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_3(divs, i32, env, i32, i32) DEF_HELPER_3(divu, i32, env, i32, i32) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 4a856e6..1e07e21 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -145,11 +145,6 @@ uint32_t helper_cmpu(uint32_t a, uint32_t b) return t; } -uint32_t helper_clz(uint32_t t0) -{ - return clz32(t0); -} - uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) { return compute_carry(a, b, cf); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index de2090a..0bb6095 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -768,7 +768,7 @@ static void dec_bit(DisasContext *dc) t_gen_raise_exception(dc, EXCP_HW_EXCP); } if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) { - gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]); + tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); } break; case 0x1e0: |