diff options
author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-05-19 15:29:17 +0100 |
---|---|---|
committer | Laurent Vivier <laurent@vivier.eu> | 2021-05-26 20:45:18 +0200 |
commit | 5e50c6c72bf8575f124ec9397411f4a2ff0d0206 (patch) | |
tree | 55651406bbf6c39962c5405995c00f1bd1b21a58 /target/m68k/translate.c | |
parent | 456a0e3b3c723d1d599d73920e98474ca9073386 (diff) | |
download | qemu-5e50c6c72bf8575f124ec9397411f4a2ff0d0206.zip qemu-5e50c6c72bf8575f124ec9397411f4a2ff0d0206.tar.gz qemu-5e50c6c72bf8575f124ec9397411f4a2ff0d0206.tar.bz2 |
target/m68k: implement m68k "any instruction" trace mode
The m68k trace mode is controlled by the top 2 bits in the SR register. Implement
the m68k "any instruction" trace mode where bit T1=1 and bit T0=0 in which the CPU
generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing each
instruction.
This functionality is used by the NetBSD kernel debugger to allow single-stepping
on m68k architectures.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'target/m68k/translate.c')
-rw-r--r-- | target/m68k/translate.c | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 10e8aba..f0c5bf9 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -124,6 +124,7 @@ typedef struct DisasContext { #define MAX_TO_RELEASE 8 int release_count; TCGv release[MAX_TO_RELEASE]; + bool ss_active; } DisasContext; static void init_release_array(DisasContext *s) @@ -197,12 +198,13 @@ static void do_writebacks(DisasContext *s) static bool is_singlestepping(DisasContext *s) { /* - * Return true if we are singlestepping either because of QEMU gdbstub - * singlestep. This does not include the command line '-singlestep' mode - * which is rather misnamed as it only means "one instruction per TB" and - * doesn't affect the code we generate. + * Return true if we are singlestepping either because of + * architectural singlestep or QEMU gdbstub singlestep. This does + * not include the command line '-singlestep' mode which is rather + * misnamed as it only means "one instruction per TB" and doesn't + * affect the code we generate. */ - return s->base.singlestep_enabled; + return s->base.singlestep_enabled || s->ss_active; } /* is_jmp field values */ @@ -323,9 +325,14 @@ static void gen_singlestep_exception(DisasContext *s) { /* * Generate the right kind of exception for singlestep, which is - * EXCP_DEBUG for QEMU's gdb singlestepping. + * either the architectural singlestep or EXCP_DEBUG for QEMU's + * gdb singlestepping. */ - gen_raise_exception(EXCP_DEBUG); + if (s->ss_active) { + gen_raise_exception(EXCP_TRACE); + } else { + gen_raise_exception(EXCP_DEBUG); + } } static inline void gen_addr_fault(DisasContext *s) @@ -6194,6 +6201,12 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->done_mac = 0; dc->writeback_mask = 0; init_release_array(dc); + + dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS); + /* If architectural single step active, limit to 1 */ + if (is_singlestepping(dc)) { + dc->base.max_insns = 1; + } } static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) |