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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-06-26 09:19:10 -0700 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-07-03 09:56:52 +1000 |
| commit | 94bf2658676be00b6f2b4db5d1788122217665b0 (patch) | |
| tree | 6121b15476d188ea80373a0d32e57f939ba5af6a /target/lm32 | |
| parent | 0f3110fa67d3c3405202104f4833f1780e1a32bb (diff) | |
| download | qemu-94bf2658676be00b6f2b4db5d1788122217665b0.zip qemu-94bf2658676be00b6f2b4db5d1788122217665b0.tar.gz qemu-94bf2658676be00b6f2b4db5d1788122217665b0.tar.bz2 | |
target/ppc: Use atomic load for LQ and LQARX
Section 1.4 of the Power ISA v3.0B states that both of these
instructions are single-copy atomic. As we cannot (yet) issue
128-bit loads within TCG, use the generic helpers provided.
Since TCG cannot (yet) return a 128-bit value, add a slot within
CPUPPCState for returning the high half of a 128-bit return value.
This solution is preferred to the helper assigning to architectural
registers directly, as it avoids clobbering all TCG live values.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/lm32')
0 files changed, 0 insertions, 0 deletions