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| author | Paolo Bonzini <pbonzini@redhat.com> | 2024-10-21 08:59:03 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-10-30 16:30:56 +0100 |
| commit | 14bde8cd7613753182baee636f216cb2d840a9e3 (patch) | |
| tree | a3ab0848b603809887b7e8099f1d02a1bce861e8 /target/i386/tcg/decode-new.c.inc | |
| parent | 15195de6a93438be99fdf9a90992c4228527130d (diff) | |
| download | qemu-14bde8cd7613753182baee636f216cb2d840a9e3.zip qemu-14bde8cd7613753182baee636f216cb2d840a9e3.tar.gz qemu-14bde8cd7613753182baee636f216cb2d840a9e3.tar.bz2 | |
target/i386: fix CPUID check for LFENCE and SFENCE
LFENCE and SFENCE were introduced with the original SSE instruction set;
marking them incorrectly as cpuid(SSE2) causes failures for CPU models
that lack SSE2, for example pentium3.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/tcg/decode-new.c.inc')
| -rw-r--r-- | target/i386/tcg/decode-new.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index 1f19371..48bf730 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -345,9 +345,9 @@ static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, [1] = X86_OP_ENTRYw(RDxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3), [2] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3 zextT0), [3] = X86_OP_ENTRYr(WRxxBASE, R,y, cpuid(FSGSBASE) chk(o64) p_f3 zextT0), - [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE2) p_00), + [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE) p_00), [6] = X86_OP_ENTRY0(MFENCE, cpuid(SSE2) p_00), - [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE2) p_00), + [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE) p_00), }; static const X86OpEntry group15_mem[8] = { |