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| author | Jing Liu <jing2.liu@intel.com> | 2022-02-16 22:04:28 -0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-03-15 11:50:50 +0100 |
| commit | 1f16764f7d4515bfd5e4ae0aae814fa280a7d0c8 (patch) | |
| tree | 8f0e3f6c59160017625e732952a043234a467a55 /target/i386/cpu.c | |
| parent | 131266b7565bd437127bd231563572696bb27235 (diff) | |
| download | qemu-1f16764f7d4515bfd5e4ae0aae814fa280a7d0c8.zip qemu-1f16764f7d4515bfd5e4ae0aae814fa280a7d0c8.tar.gz qemu-1f16764f7d4515bfd5e4ae0aae814fa280a7d0c8.tar.bz2 | |
x86: Add AMX XTILECFG and XTILEDATA components
The AMX TILECFG register and the TMMx tile data registers are
saved/restored via XSAVE, respectively in state component 17
(64 bytes) and state component 18 (8192 bytes).
Add AMX feature bits to x86_ext_save_areas array to set
up AMX components. Add structs that define the layout of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-3-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/i386/cpu.c')
| -rw-r--r-- | target/i386/cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0f3c477..ec35dd1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1402,6 +1402,14 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { [XSTATE_PKRU_BIT] = { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, .size = sizeof(XSavePKRU) }, + [XSTATE_XTILE_CFG_BIT] = { + .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, + .size = sizeof(XSaveXTILECFG), + }, + [XSTATE_XTILE_DATA_BIT] = { + .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, + .size = sizeof(XSaveXTILEDATA) + }, }; static uint32_t xsave_area_size(uint64_t mask) |